1. Field of the Invention
The present invention generally relates to data processing systems and, more particularly, to an improved data processing system topology. Still more particularly, the present invention refers to an improved data processing system topology utilizing a Fully Interconnected System Architecture (FISA).
2. Description of the Related Art
Increasing performance and reliability and decreasing component size or required space are important aspects of data processing system development. System developers continually search for ways to increase the system processing performance while maintaining reliability in the transmission processes, without incurring additional hardware costs. Often such development is focussed on faster overall processors. However, this development may also center around increasing the capacity of data buses and other buses or increasing the propagation speed between system components. Those skilled in the art are familiar with the trend of increasing the capacities of the buses within a data processing system to improve efficiency of the system.
An integrated circuit (I/C) is a device consisting of a number of connected circuit elements, such as transistors and resistors and functional combinations thereof, fabricated on a single chip of silicon crystal or other semiconductor material. In integrated circuit fabrication technology, an ever-increasing number of integrated circuit devices are being built into chips. This growing number of devices requires a correspondingly larger amount of space and greater numbers of input/output (I/O) connections to and from the chip.
Typically, the I/O connections are conductive metal pathways, connected to the metal leads protruding from the edges of the I/C chips. These I/O connections are referred to as data buses and each set of parallel data buses is characterized by the number of bits it can transfer at a single time, equivalent to the number of parallel conducting paths (which can be thought of as wires) wired to the metal leads of an integrated circuit chip. The number of these parallel conducting paths is typically referred to as the width of the bus.
The miniaturization of integrated circuits has made it possible to pack more and more data processing power into a small volume. The increased data processing power has made it necessary to provide more metal leads (I/O connections) for each I/C chip. However, the small volume of the I/C chip (i.e., small edge surface area) has also resulted in such metal leads being tightly spaced. Consequently, on a printed circuit board utilizing modern integrated circuits, the I/O connections of the I/C chips are physically very close. Accordingly, the conductive paths, at least where they connect with individual I/O connections, are also in very close proximity to each other.
I/C chips are manufactured with different numbers of metal layers. One of the more popular chip topologies has eight metal layers with the layers configured in a criss-crossed manner. The intra-chip components, which may comprise of a processor, higher level cache (or caches), and cache controller are typically located within the lower layers of metal and require large amounts of transistors. Thus the lower metal layers of a chip are primarily used to connect transistors and other logic components.
While the limit to the number of conductors practicably connected in parallel is rapidly being approached, the processing power of integrated circuits continues to increase while the volume of the I/C chip continues to shrink.
One common I/C chip is the processor chip utilized within a data processing system. Typically, processors and higher level caches are located on a processor chip, which is designed with a plurality of buses extending off of the edges of the chip. Current chip manufacture allows for the placement of multiple processors on a single chip. These chips in turn have a set of dedicated buses through which the processors communicate to external components such as memory, input/output (I/O) devices and other processors. These buses provide the connection (via the system bus) required by the processor to external (i.e., off-chip) components such as system memory and other processors in a multi-chip configuration. Current designs of data processing systems involve coupling together several of these processor chips to create multi-processor data processing systems (or symmetric multiprocessor (SMP) data processing systems).
The improvements in silicon technology result in the reduction in size of the chip components (eg., transistors) and a corresponding increase in processor frequencies. The increased processor frequencies in turn lead to higher levels of cache misses. One way of reducing the number of cache misses, while utilizing the extra intra-chip space due to smaller processor transistors, is by increasing the size of the intra-chip L2 caches. This necessitates larger numbers of transistors which make up the primary component of caches. The (lower) metal layers with the resulting larger L2 caches are therefore extremely inundated with transistor interconnects. In contrast, the upper metal layers of the chip are traditionally free of transistors and/or sparingly utilized.
Traditionally data processing systems were designed with single processor chips having one or more central processing units (CPU) and a tri-state multi-drop bus. In these traditional single chip data processing systems, all bus interfaces were utilized by memory, other caches, and input/output (I/O) devices. With the fast growth of multi-processor data processing systems, building larger scalable SMPs requires the ability to hook up multiple numbers of these chips utilizing the bus interface.
One recent development in improving efficiency of communication between chip components with external components, such as other chips and memory, without necessarily requiring larger numbers of on-chip connectors is the utilization of an off-chip switch connector. Off-chip switches typically are comprised of large masses of wire interconnects which provide multiple point-to-point connections between chip components and external components. This topology is referred to as the tri-state point-to-point bus topology.
In more recent SMP topologies, the conventional tri-state system buses have been replaced by switches. Switches typically comprise of a large number of connectors which provide direct connection between the processor chip and each of the external components coupled to it. Switch topologies provide faster/direct connection between components leading to more efficient and faster processing. In these switch based systems, the switches are located on the processing system""s motherboard and are designed as separate and individual components on the data processing system. Switches are very wire intensive, and requires large amounts of silicon and space on the data processing system""s motherboard.
Another topology implemented within the industry is the uni-directional point-to-point bus topology which also utilizes a switch but provides individual buses to connect each system component to another. Although this approach provides higher frequency buses, the limitations of a switch topology, as previously described, still exist.
The present invention recognizes that it would therefore be desirable and advantageous to have a data processing system topology which allows for more efficient routing of signals and/or data between processor chip components and external components to the processor chip. It would also be desirable to have a data processing system which implements a more efficient tri-state or point-to-point bus interconnect without the limitations of requiring separate space on the processor motherboard or additional chip space (i.e., without incurring additional hardware costs). It would further be desirable to have a fully interconnected system architecture which provided processors with larger overall interconnect bandwidth and reduced latencies to improve overall system performance.
It is therefore one object of the present invention to provide an improved data processing system.
It is another object of the present invention to provide an improved data processing system topology.
It is yet another object of the present invention to provide to an improved data processing system topology with lower latencies and increased data bandwidths utilizing a Fully Interconnected System Architecture (FISA).
The foregoing objects are achieved as follows. A Fully Interconnected System Architecture (FISA) is described for an improved data processing system. The data processing system topology has a processor chip and external components to the processor chip, such as memory and input/output (I/O) and other processor chips. The processor chip is interconnected to the external components via a point-to-point bus topology controlled by an intra-chip integrated, distributed switch (IDS) controller. The IDS controller provides the chip with the functionality to provide a single bus to each external component and provides an overall total bandwidth greater than traditional topologies while reducing latencies between the processor and the external components. The design of the processor chip with the intra-chip IDS controller provides a pseudo xe2x80x9cdistributed switchxe2x80x9d which may separately access distributed external components, such as memory and I/Os, etc.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.